1. Field of the Invention
The present invention relates to a wiring layout apparatus, a wiring layout method, and a wiring layout program for a semiconductor integrated circuit, and particularly to a wiring layout apparatus, a wiring layout method, and a wiring layout program, for a semiconductor integrated circuit, configured to lay out wiring strip conductors whose width and the spaces therebetween are as small as the resolution limit of an exposure apparatus.
2. Description of the Related Art
To date, in designing a wiring layout for a semiconductor integrated circuit, based on the assumption that the respective characteristics of circuit elements and parasitic elements on the chip are approximately homogeneous, the design has been performed with a margin. In other words, on the assumption that, even though some variations exist in the characteristics of the elements on the chip, the variations fall within a tolerance range, designing of a wiring layout for a semiconductor integrated circuit has been performed in consideration only of a desirable timing specification.
In recent years, due to promotion of device miniaturization, the dimension of a strip conductor such as a wiring strip conductor drawn on a semiconductor substrate has become smaller than the light-source wavelength of a drawing exposure apparatus; therefore, it has become difficult to process wiring strip conductors in accordance with intended design sizes. In particular, due to the miniaturization and the high-density integration of a mask pattern, pattern arrangement and adjacency relationship affect largely each other in a process of forming strip conductors through photolithography or etching processing. In order to cope with the foregoing problem, the optical proximity correction processing (hereinafter, described as OPC processing), in which a correction pattern is preliminarily added to a designed pattern, is generally performed so that the size of a processed strip conductor becomes equal to the desirable size of the strip conductor.
However, in order to accurately realize a densely integrated layout pattern, through the OPC processing, considerably large data processing time is required. In addition, depending on the combination of the shapes of adjacent strip conductors, a variation in processing size is caused, and a parasitic capacitance and a resistance also vary; thus, a delay, of a signal that propagates on the wiring strip conductors, which is a critical path in timing design, is caused to vary. In other words, because, in the OPC processing, the designed pattern is not sufficiently corrected, the sizes of the processed strip conductors do not become the desirable size, whereby electrical characteristics, especially a delay, of a signal that propagates on the wiring strip conductors, which is a critical path in timing design, is caused to vary. Accordingly, it has been a problem that a chip is produced that cannot realize a preliminarily set operating frequency, thereby deteriorating the yield rate of the chip.
As measures for the variation in the size of a strip conductor, semiconductor integrated circuit devices have been proposed (e.g., refer to Japanese Patent Application Laid-Open No. 2005-303089) in which, by adding dummy strip conductors each having a predetermined regularity to a designed pattern, the variation in the size of a strip conductor due to processing is suppressed.
However, it has been a problem that, because, with the miniaturization of devices in recent years, wiring has come to be densely formed in an overall chip, a vacant space where no wiring is laid has become very small, whereby, it is difficult to add dummy strip conductors to a designed pattern, as is the case with the semiconductor integrated circuit device disclosed in Japanese Patent Application Laid-Open No. 2005-303089.